Numonyx™ StrataFlash® Cellular Memory (M18)
4.6
Signal Descriptions, x16 Split Bus
Table 9:
Signal Descriptions, x16 Split Bus, Non-Mux (Sheet 1 of 4)
Symbol
Type
Signal Descriptions
Notes
Address and Data Signals, Non-Mux
FLASH ADDRESS: Flash device signals.
Dedicated address inputs for Flash memory die during read and write operations.
•
•
•
•
•
2-Gbit: AMAX = A26
1-Gbit: AMAX = A25
512-Mbit: AMAX = A24
256-Mbit: AMAX = A23
128-Mbit: AMAX = A22
F-A[MAX:0]
Input
Input
Unused address inputs are RFU.
LPSDRAM ADDRESS: LSPDRAM device signals.
Dedicated address inputs for LPSDRAM memory die during read and write operations.
•
•
•
A[12:0] are the row and A[9:0] are the column addresses for 512-Mbit LPSDRAM.
A[12:0] are the row and A[8:0] are the column addresses for 256-Mbit LPSDRAM.
A[11:0] are the row and A[8:0] are the column addresses for 128-Mbit LPSDRAM.
D-A[MAX:0]
Unused address inputs are RFU.
FLASH DATA INPUT/OUTPUTS: Flash device signals.
•
•
•
Inputs Flash data and commands during write cycles.
Outputs data during read cycles.
Data signals are High-Z when the device is deselected or its output is disabled.
Input/
Output
F-DQ[15:0]
D-DQ[15:0]
LPSDRAM DATA INPUT/OUTPUTS: LPSDRAM device signals.
•
•
•
Inputs LPSDRAM data and commands during write cycles.
Outputs data during read cycles.
Data signals are High-Z when the device is deselected or its output is disabled.
Input/
Output
Address and Data Signals, A/D Mux
ADDRESS: Flash device signals.
Shared address inputs for all Flash memory die during Read and Write operations.
•
•
•
•
•
2-Gbit: AMAX = A26
1-Gbit: AMAX = A25
512-Mbit: AMAX = A24
256-Mbit: AMAX = A23
128-Mbit: AMAX = A22
F-A[MAX:16]
Input
Unused address inputs should be treated as RFU.
ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: AD-Mux flash lower address and data
signals; LPSDRAM data signals.
During AD-Mux flash Write cycles, ADQ[15:0] are used to input the lower address followed by
commands or write-data.
During AD-Mux flash Read cycles, ADQ[15:0] are used to input the lower address followed by
read-data output.
Input /
Output
F-ADQ[15:0]
During LPSDRAM accesses, ADQ[15:0] are used to input commands and write-data during
Write cycles or to output read-data during Read cycles.
During NAND accesses, ADQ[7:0] are used to input commands, address, or write-data, and to
output read-data.
ADQ[15:0] are High-Z when the flash is deselected or its output is disabled.
Control Signals
Datasheet
38
April 2008
309823-10
NUMONYX [ NUMONYX B.V ]
