Numonyx™ StrataFlash® Cellular Memory (M18)
7.3
Write Specifications
The M18 device includes specifications for different lithographies, densities, and
frequencies. For additional information on combinations, see Table 4, “M18 Product
Litho/Density/Frequency Combinations” on page 10 in the Section 2.0, “Functional
Description.
Table 22: AC Write Specifications
Number
W1
Symbol
tPHWL
Parameter (1, 2)
Min
Max
Units
Notes
RST# high recovery to WE# low
CE# setup to WE# low
150
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3
1,2
W2
tELWL
0
W3
tWLWH
tDVWH
tAVWH
tWHEH
tWHDX
tWHAX
tWHWL
tVPWH
tQVVL
tQVBL
tBHWH
tWHGL
tVLWH
tWHQV
WE# write pulse width low
Data setup to WE# high
40
1,2,4
W4
40
W5
Address setup to WE# high
CE# hold from WE# high
Data hold from WE# high
Address hold from WE# high (non-mux only)
WE# pulse width high
40
W6
0
1,2
W7
0
W8
0
W9
20
1,2,5
W10
W11
W12
W13
W14
W15
W16
VPP setup to WE# high
200
VPP hold from Status read
WP# hold from Status read
WP# setup to WE# high
0
1,2,3,7
0
200
WE# high to OE# low
0
1,2,8
1,2
ADV# low to WE# high (AD-Mux only)
WE# high to read valid
55
tAVQV+30
1,2,3,9
Write to Synchronous Read Specifications
W19
W27
W28
tWHCH
tWHEL
tWHVL
WE# high to Clock high
WE# high to CE# low
WE# high to ADV# low
15
9
—
—
—
ns
ns
ns
1,2,3,6,9
1,2,3,6,9
1,2,3,6,9
7
Bus Write with Active Clock Specifications
W21
W22
tVHWL
tCHWL
ADV# high to WE# low
Clock high to WE# low
—
—
27
27
ns
ns
1,2,10,11
Notes:
1.
2.
3.
4.
Write timing characteristics during erase suspend are the same as write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH
.
5.
6.
Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
(whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL).
tWHCH must be met when transitioning from a write cycle to a synchronous burst read. In addition there must be a CE#
toggle after WE# goes high.
7.
8.
9.
VPP and WP# should be at a valid level until erase or program success is determined.
When doing a Read Status operation following any command that alters the Status Register data, W14 is 20ns.
Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to reflect
this change.
10.
11.
This specification is applicable only if the part is configured in synchronous mode and an active clock is running. Either
tVHWL or tCHWL must be met depending on the whether the address is latched on ADV# or CLK.
These specifications are not applicable to 133 MHz devices.
Datasheet
60
April 2008
309823-10
NUMONYX [ NUMONYX B.V ]
