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JS48F4400P0Z3W0 参数 Datasheet PDF下载

JS48F4400P0Z3W0图片预览
型号: JS48F4400P0Z3W0
PDF下载: 下载PDF文件 查看货源
内容描述: StrataFlash㈢蜂窝内存 [StrataFlash㈢ Cellular Memory]
分类和应用: 蜂窝
文件页数/大小: 139 页 / 2133 K
品牌: NUMONYX [ NUMONYX B.V ]
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Numonyx™ StrataFlash® Cellular Memory (M18)  
8.0  
NOR Flash Bus Interface  
The flash device uses low-true control signal inputs, and is selected by asserting the  
chip enable (CE#) input. The output enable (OE#) input is asserted for read  
operations, while the write enable (WE#) input is asserted for write operations. OE#  
and WE# should never be asserted at the same time; otherwise, indeterminate device  
operation will result. All bus cycles to or from the flash memory conform to standard  
microcontroller bus cycles.  
Commands are written to the device to control all operations.  
Table 27 shows the logic levels that must be applied to the control-signal inputs of the  
device for the various bus operations.  
Table 27: Flash Memory Control Signals  
Operation  
RST#  
DPD2  
CE#1  
OE#1  
WE#1  
Address1  
Data I/O  
Reset  
Read  
Low  
High  
High  
High  
High  
High  
X
X
X
X
Valid  
X
High-Z  
Output  
High-Z  
Low  
Low  
Low  
High  
High  
High  
Output Disable  
High  
High  
High  
High  
Low  
High  
High  
Valid  
Valid  
Input  
Input  
Write  
Low  
Standby  
High  
High  
High  
Low  
High  
High  
X
X
X
X
X
X
High-Z  
High-Z  
Deep Power-Down  
Notes:  
1.  
2.  
X = Don’t care (High or Low)  
DPD polarity determined by ECR14. Shown low-true here.  
8.1  
Bus Reads  
To perform a read operation, both CE# and OE# must be asserted; #RST# and WE#  
must be deasserted. OE# is the data-output control and when asserted, the output  
data is driven on to the data I/O bus. All read operations are independent of the  
voltage level on VPP.  
The Automatic Power Savings (APS) feature provides low power operation following  
reads during active mode. After data is read from the memory array and the address  
lines are quiescent, APS automatically places the device into standby. In APS, device  
current is reduced to ICCAPS  
.
The device supports two read configurations:  
• Asynchronous reads. RCR15 = 1. This is the default configuration after power-up/  
reset.  
— Non-multiplexed devices support asynchronous page-mode reads. AD-  
Multiplexed devices support only asychronous single-word reads.  
• Synchronous Burst reads. RCR15 = 0.  
April 2008  
309823-10  
Datasheet  
71