Numonyx™ StrataFlash® Cellular Memory (M18)
Table 47: Program OTP Register Command Bus Cycles
Setup Write Cycle
Command
Confirm Write Cycle
Address Bus Data Bus
OTP Register Address Register Data
Address Bus
Data Bus
Program OTP Register
Device Address
00C0h
Attempting to program an OTP register outside of the OTP register space causes a
program error (SR4 = 1). Attempting to program a locked OTP Register causes a
program error and a lock error (SR4 = 1, SR1 = 1).
To read from any of the OTP registers, first issue the Read Device Information
command. Then read from the desired OTP Register address offset. For additional
details, refer to Section 9.4.3, “Read Device Information” on page 82.
9.11.3
Global Main-Array Protection
Global main-array protection can be implemented by controlling VPP. When
programming or erasing main-array blocks, VPP must be equal to, or greater than VPPL
(min). When VPP is below VPPLK, program or erase operations are inhibited, thus
providing absolute protection of the main array.
Various methods exist for controlling VPP, ranging from simple logic control to off-board
voltage control. Figure 51 shows example VPP supply connections that can be used to
support program/erase operations and main-array protection.
Figure 51: Example VPP Supply Connections
VCC
VCC
VPP
VCC
VCC
VPP
VPPH
VPPL
PROT#
≤ 10ΚΩ
•
•
Factory Programming: VPP = VPPH
Program/Erase Protection: VPP ≤ VPPLK
•
•
Program/Erase Enable: PROT# = VIH
Program/Erase Protection: PROT# = VIL
VCC
VCC
VPP
VCC
VCC
VPP
VPPL
VPPL
VPPH
•
•
Low-Voltage Programming: VPP = VPPL
- or-
Factory Programming: VPP = VPPH
•
•
Low-Voltage Programming: VPP = VCC
Program/Erase Protection: None
April 2008
309823-10
Datasheet
99
NUMONYX [ NUMONYX B.V ]
