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M25P16-VMW6TG 参数 Datasheet PDF下载

M25P16-VMW6TG图片预览
型号: M25P16-VMW6TG
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位串行闪存, 75 MHz的SPI总线接口 [16 Mbit, serial Flash memory, 75 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 55 页 / 1057 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25P16  
Revision history  
13  
Revision history  
Table 23. Document revision history  
Date  
Revision  
Changes  
Target Specification Document written  
16-Jan-2002  
0.1  
Clarification of descriptions of entering Standby Power mode from Deep  
Power-down mode, and of terminating an instruction sequence or data-  
out sequence.  
23-Apr-2002  
0.4  
0.5  
ICC2(max) value changed to 10µA  
Typical Page Program time improved. Write Protect setup and hold times  
specified, for applications that switch Write Protect to exit the Hardware  
Protection mode immediately before a WRSR, and to enter the Hardware  
Protection mode again immediately after  
13-Dec-2002  
15-May-2003  
0.6  
0.7  
0.8  
MLP8 package added  
50MHz operation, and RDID instruction added. Published internally, only  
8x6 MLP8 and SO16(300 mil) packages added  
20-Jun-2003  
24-Sep-2003  
tPP, tSE and tBE revised. SO16 package code changed. Output Timing  
Reference Voltage changed. Document promoted to Preliminary Data.  
1.0  
2.0  
3.0  
Table of contents, warning about exposed paddle on MLP8, and Pb-free  
options added.  
24-Nov-2003  
17-May-2004  
Value of tVSL(min) and tBE(typ) changed. Change of naming for VDFPN8  
packages. Document promoted to full Datasheet.  
MLP8(5x6) package removed. Soldering temperature information  
clarified for RoHS compliant devices. Device Grade clarified  
Notes 1 and 2 removed from Table 22: Ordering information scheme.  
Small text changes.  
Read Identification (RDID), Deep Power-down (DP) and Release from  
Deep Power-down and Read Electronic Signature (RES) instructions,  
and Active Power, Standby Power and Deep Power-down modes  
paragraph clarified.  
01-Apr-2005  
01-Aug-2005  
20-Oct-2005  
4.0  
5.0  
6.0  
Updated Page Program (PP) instructions in Page programming, Page  
Program (PP) and Table 15: AC characteristics (Grade 6).  
VFQFPN8 package added (see Figure 27: VFQFPN8 (MLP8) 8-lead very  
thin fine pitch quad flat package no lead, 6 × 5 mm, package outline and  
Table 17: VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package  
no lead, 6 × 5 mm, package mechanical data).  
All packages are ECOPACK®. “Blank” option removed under Plating  
Technology.  
SO8 Narrow and SO8 Wide packages added (see Section 11: Package  
mechanical). VDFPN8 package updated (see Table 18: VDFPN8 (MLP8)  
8-lead very thin dual flat package no lead, 8 × 6 mm, package  
mechanical data). Note 1 added to Table 22: Ordering information  
scheme.  
27-Feb-2006  
04-Jul-2006  
7
8
Figure 4: Bus master and memory devices on the SPI bus updated and  
Note 2 added. SO8N package specifications updated (see Figure 29 and  
Table 19). Small text changes.  
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