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M25PE10-VMP6TG 参数 Datasheet PDF下载

M25PE10-VMP6TG图片预览
型号: M25PE10-VMP6TG
PDF下载: 下载PDF文件 查看货源
内容描述: 1和2兆,页擦除串行闪存与字节变性, 75兆赫的SPI总线,标准引脚 [1 and 2 Mbit, page-erasable serial Flash memories with byte alterability, 75 MHz SPI bus, standard pinout]
分类和应用: 闪存
文件页数/大小: 64 页 / 1231 K
品牌: NUMONYX [ NUMONYX B.V ]
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DC and AC parameters  
M25PE20, M25PE10  
(1) (2)  
Table 24. AC characteristics (75 MHz operation, T9HX (0.11 µm) process  
)
Test conditions specified in Table 16 and Table 17  
Symbol  
Alt.  
Parameter  
Min.  
Typ.  
Max.  
Unit  
Clock frequency for the following instructions:  
FAST_READ, RDLR, PW, PP, WRLR, PE, SE, SSE,  
DP, RDP, WREN, WRDI, RDSR, WRSR  
fC  
fR  
fC  
D.C.  
75  
33  
MHz  
Clock frequency for READ instructions  
D.C.  
6
MHz  
ns  
(3)  
tCH  
tCLH Clock High time  
(2)  
tCL  
tCLL  
Clock Low time  
6
ns  
Clock Slew Rate 2 (peak to peak)  
0.1  
5
V/ns  
ns  
tSLCH  
tCHSL  
tDVCH  
tCHDX  
tCHSH  
tSHCH  
tSHSL  
tCSS S Active Setup time (relative to C)  
S Not Active Hold time (relative to C)  
tDSU Data In Setup time  
5
ns  
2
ns  
tDH  
Data In Hold time  
5
ns  
S Active Hold time (relative to C)  
S Not Active Setup time (relative to C)  
5
ns  
5
ns  
tCSH S Deselect time  
100  
ns  
(4)  
tSHQZ  
tDIS  
tV  
Output Disable time  
8
ns  
tCLQV  
Clock Low to Output Valid under 30 pF/10 pF  
Output Hold time  
8/6  
ns  
tCLQX  
tHO  
0
ns  
(5)  
tWHSL  
Write Protect Setup time  
20  
ns  
(4)  
tSHWL  
Write Protect Hold time  
100  
ns  
(4)  
tDP  
S to Deep Power-down  
3
µs  
(4)  
tRDP  
S High to Standby mode  
30  
15  
23  
µs  
tW  
(6)  
Write Status Register cycle time  
Page Write cycle time (256 bytes)  
Page Program cycle time (256 bytes)  
3
ms  
ms  
tPW  
11  
0.8  
(5)  
tPP  
3
ms  
int(n/8) ×  
0.025(7)  
Page Program cycle time (n bytes)  
tPE  
tSE  
tSSE  
tBE  
Page Erase cycle time  
Sector Erase cycle time  
SubSector Erase cycle time  
Bulk Erase cycle time  
10  
1.5  
80  
20  
5
ms  
s
150  
10  
ms  
s
4.5  
1. See Important note on page 6.  
2. Details of how to find the technology process in the marking are given in AN1995, see also Section 13: Ordering  
information.  
3. tCH + tCL must be greater than or equal to 1/ fC.  
4. Value guaranteed by characterization, not 100% tested in production.  
5. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.  
6. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence  
including all the bytes versus several sequences of only a few bytes (1 n 256).  
7. int(A) corresponds to the upper integer part of A. E.g. int(12/8) = 2, int(32/8) = 4 int(15.3) =16.  
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