Description
M25PE20, M25PE10
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Description
The M25PE20 and M25PE10 are 2 Mbit (256 Kb × 8 bit) and 1 Mbit (128 Kb × 8 bit) serial
paged Flash memories, respectively. They are accessed by a high speed SPI-compatible
bus.
The memories can be written or programmed 1 to 256 bytes at a time, using the Page Write
or Page Program instruction. The Page Write instruction consists of an integrated Page
Erase cycle followed by a Page Program cycle.
The M25PE20 memory is organized as 4 sectors, each containing 256 pages. Each page is
256 bytes wide. Thus, the whole memory can be viewed as consisting of 1024 pages, or
262,144 bytes.
The M25PE10 memory is organized as 2 sectors, each containing 256 pages. Each page is
256 bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or
131, 072 bytes.
The memories can be erased a page at a time, using the Page Erase instruction, a
subsector at a time, using the SubSector Erase instruction, a sector at a time, using the
Sector Erase instruction or as a whole, using the Bulk Erase instruction.
The memory can be write protected by either hardware or software using a mix of volatile
and non-volatile protection features, depending on the application needs. The protection
granularity is of 64 Kbytes (sector granularity).
Important note
This datasheet details the functionality of the M25PE20 and M25PE10 devices, based on
the previous T7X process or based on the current T9HX process (available since July 2007).
Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of
2008.
What are the changes?
The M25PE10/M25PE20 in T9HX process offers the following additional features:
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the whole memory array is partitioned into 4-Kbyte subsectors
five new instructions: Write Status Register (WRSR), Write to Lock Register (WRLR),
Read Lock Register (RDLR), 4-Kbyte SubSector Erase (SSE) and Bulk Erase (BE)
Status Register: 3 bits can be written (BP0, BP1, SRWD)
WP input (pin 3): write protection limits are extended, depending on the value of the
BP0, BP1, SRWD bits. The WP write protection remains the same if bits (BP1, BP0)
are set to (0, 1) or (1, 0)
VFQFPN8 6 × 5 mm package added.
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