NXP Semiconductors
TJA1042
High-speed CAN transceiver with Standby mode
6.2 Fail-safe features
6.2.1 TXD dominant time-out function
A ‘TXD dominant time-out’ timer is started when pin TXD is set LOW. If the LOW state on
pin TXD persists for longer than t
to(dom)TXD
, the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD is set to HIGH.
The TXD dominant time-out time also defines the minimum possible bit rate of 40 kbit/s.
6.2.2 Bus dominant time-out function
In Standby mode a 'bus dominant time-out' timer is started when the CAN bus changes
from recessive to dominant state. If the dominant state on the bus persists for longer than
t
to(dom)bus
, the RXD pin is reset to HIGH. This function prevents a clamped dominant bus
(due to a bus short-circuit or a failure in one of the other nodes on the network) from
generating a permanent wake-up request. The bus dominant time-out timer is reset when
the CAN bus changes from dominant to recessive state.
6.2.3 Internal biasing of TXD and STB input pins
Pins TXD and STB have internal pull-ups to
V
IO
to ensure a safe, defined state in case
one or both of these pins are left floating.
6.2.4 Undervoltage detection on pins V
CC
and V
IO
Should V
CC
drop below the V
CC
undervoltage detection level, V
uvd(VCC)
, the transceiver
will switch to Standby mode. The logic state of pin STB will be ignored until V
CC
has
recovered.
Should
V
IO
drop below the
V
IO
undervoltage detection level, V
uvd(VIO)
, the transceiver will
switch off and disengage from the bus (zero load) until V
IO
has recovered.
6.2.5 Over-temperature protection
The output drivers are protected against overtemperature conditions. If the virtual junction
temperature exceeds the shutdown junction temperature, T
j(sd)
, the output drivers will be
disabled until the virtual junction temperature falls below T
j(sd)
and TXD becomes
recessive again. Including the TXD condition ensures that output driver oscillation due to
temperature drift is avoided.
6.3 SPLIT output pin and V
IO
supply pin
Two versions of the TJA1042 are available, only differing in the function of a single pin. Pin
5 is either a SPLIT output pin or a V
IO
supply pin.
6.3.1 SPLIT pin
Using the SPLIT pin on the TJA1042T in conjunction with a split termination network (see
and
can help to stabilize the recessive voltage level on the bus. This will
reduce EME in networks with DC leakage to ground (e.g. from deactivated nodes with
poor bus leakage performance). In Normal mode, pin SPLIT delivers a DC output voltage
of 0.5V
CC
. In Standby mode or when V
CC
is off, pin SPLIT is floating.
TJA1042_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 8 July 2009
6 of 20
PHILIPS [ NXP SEMICONDUCTORS ]
