74HC74
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
25_C
(V)
v 85_C v 125_C
Symbol
Parameter
Test Conditions
Unit
V
2.0
3.0
4.5
6.0
1.5
2.1
V
Minimum High−Level Input
V
= 0.1 V or V – 0.1 V
1.5
2.1
1.5
2.1
IH
out
CC
Voltage
|I | v 20 mA
out
3.15
4.2
3.15
4.2
3.15
4.2
V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
V
V
Maximum Low−Level Input
Voltage
V
= 0.1 V or V – 0.1 V
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
IL
out
CC
|I | v 20 mA
out
V
Minimum High−Level Output
Voltage
V
in
= V or V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
OH
IH
|I | v 20 mA
out
V
= V or V
|I | v 2.4 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
in
IH
IL
out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
V
V
Maximum Low−Level Output
V
in
= V or V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
OL
IH
IL
Voltage
|I | v 20 mA
out
V
= V or V
|I | v 2.4 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
in
IH
IL
out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
I
Maximum Input Leakage Current
V
V
= V or GND
6.0
6.0
±0.1
±1.0
±1.0
mA
mA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
2.0
20
80
= V or GND
CC
in
CC
I
= 0 mA
out
NOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
25_C
(V)
v 85_C v 125_C
Symbol
Parameter
Unit
f
MHz
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
max
24
ns
ns
ns
pF
t
t
t
,
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
3.0
4.5
6.0
100
75
20
125
90
25
150
120
30
PLH
t
PHL
17
21
26
,
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
105
80
21
130
95
26
160
130
32
PLH
t
PHL
18
22
27
,
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
TLH
t
THL
19
C
in
Maximum Input Capacitance
—
10
10
10
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V = 5.0 V
CC
32
C
PD
Power Dissipation Capacitance (Per Flip−Flop)*
pF
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
. For load considerations, see Chapter 2 of the
D
PD CC
CC CC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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