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MC100E457FNG 参数 Datasheet PDF下载

MC100E457FNG图片预览
型号: MC100E457FNG
PDF下载: 下载PDF文件 查看货源
内容描述: 5V ECL三差分2 : 1多路复用器 [5V ECL Triple Differential 2:1 Multiplexer]
分类和应用: 复用器
文件页数/大小: 9 页 / 136 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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MC10E457, MC100E457
5V ECL Triple Differential
2:1 Multiplexer
Description
The MC10E457/100E457 is a 3-bit differential 2:1 multiplexer. The
fully differential data path makes the device ideal for multiplexing low
skew clock or other skew sensitive signals.
The higher frequency outputs provide the device with a > 1.0 GHz
bandwidth to meet the needs of the most demanding system clock.
Both, separate selects and a common select, are provided to make
the device well suited for both data path and random logic
applications.
The differential inputs have internal clamp structures which will
force the Q output of a gate in an open input condition to go to a LOW
state. Thus, inputs of unused gates can be left open and will not affect
the operation of the rest of the device. Note that the input clamp will
take affect only if both inputs fall 2.5 V below V
CC
.
The 100 Series contains temperature compensation.
Multiple V
BB
pins are provided to ease AC coupling input signals.
The V
BB
pins, internally generated voltage supply pins, are available
to this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
http://onsemi.com
PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1 28
MCxxxE457FNG
AWLYYWW
Differential D and Q; V
BB
available
700 ps Max. Propagation Delay
High Frequency Outputs
Separate and Common Select
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
−4.2
V to
−5.7
V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 218 devices
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
November, 2006
Rev. 8
1
Publication Order Number:
MC10E457/D