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MC100EP16VSD 参数 Datasheet PDF下载

MC100EP16VSD图片预览
型号: MC100EP16VSD
PDF下载: 下载PDF文件 查看货源
内容描述: 评估板手册高频SOIC 8 [Evaluation Board Manual for High Frequency SOIC 8]
分类和应用: 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
文件页数/大小: 20 页 / 203 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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ECLSOIC8EVB
Evaluation Board Manual
for High Frequency SOIC 8
http://onsemi.com
EVALUATION BOARD MANUAL
INTRODUCTION
ON Semiconductor has developed an evaluation board for
the devices in 8−lead SOIC package. These evaluation
boards are offered as a convenience for the customers
interested in performing their own engineering assessment
on the general performance of the 8−lead SOIC device
samples. The board provides a high bandwidth 50
W
controlled impedance environment. The pictures in Figure 1
show the top and bottom view of the evaluation board, which
can be configured in several different ways, depending on
device under test (See Table 1. Configuration List).
This evaluation board manual contains:
Information on 8−lead SOIC Evaluation Board
Assembly Instructions
Appropriate Lab Setup
Bill of Materials
This manual should be used in conjunction with the device
data sheet, which contains full technical details on the device
specifications and operation.
Board Lay−Up
The 8−lead SOIC evaluation board is implemented in four
layers with split (dual) power supplies (Figure 2.
Evaluation Board Lay−up). For standard ECL lab setup and
test, a split (dual) power supply is essential to enable the
50
W
internal impedance in the oscilloscope as a termination
for ECL devices. The first layer or primary trace layer is
0.008″ thick Rogers RO4003 material, which is designed to
have equal electrical length on all signal traces from the
device under the test (DUT) to the sense output. The second
layer is the 1.0 oz copper ground plane and a portion of the
plane is the V
EE
power plane. The FR4 dielectric material is
placed between second and third layer and between third and
fourth layer. The third layer is also 1.0 oz copper ground
plane and a portion of this layer is V
CC
power plane. The
fourth layer is the secondary trace layer.
Figure 1. Top and Bottom View of the 8−lead SOIC Evaluation Board
©
Semiconductor Components Industries, LLC, 2004
1
August, 2004 − Rev. 1
Publication Order Number:
ECLSOIC8EVB/D