MC10ELT22, MC100ELT22
5.0 V Dual TTL to Differential
PECL Translator
The MC10ELT/100ELT22 is a dual TTL to differential PECL
translator. Because PECL (Positive ECL) levels are used only +5 V
and ground are required. The small outline 8-lead package and the low
skew, dual gate design of the ELT22 makes it ideal for applications
which require the translation of a clock and a data signal.
Features
http://onsemi.com
MARKING
DIAGRAMS*
8
1
SO−8
D SUFFIX
CASE 751
1
8
HLT22
ALYW
G
8
KLT22
ALYW
G
•
•
•
•
•
•
•
1.2 ns Typical Propagation Delay
< 300 ps Typical Output to Output Skew
PNP TTL Inputs for Minimal Loading
Flow Through Pinouts
Operating Range: V
CC
= 4.75 V to 5.25 V with GND = 0 V
No Internal Input Pulldown Resistors
Pb−Free Packages are Available
1
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
HT22
ALYWG
G
1
8
KT22
ALYWG
G
1
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional information, see Application Note
AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
November, 2006
−
Rev. 9
1
Publication Order Number:
MC10ELT22/D
ONSEMI [ ON SEMICONDUCTOR ]
