MC100ELT23
5 V Dual Differential PECL
to TTL Translator
Description
The MC100ELT23 is a dual differential PECL to TTL translator.
Because PECL (Positive ECL) levels are used, only +5 V and ground
are required. The small outline 8-lead package and the dual gate
design of the ELT23 makes it ideal for applications which require the
translation of a clock and a data signal.
The PECL inputs are differential; therefore, the MC100ELT23 can
accept any standard differential PECL input referenced from a V
CC
of
5.0 V.
Features
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MARKING DIAGRAMS*
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
8
8
1
TSSOP−8
DT SUFFIX
CASE 948R
1
DFN8
MN SUFFIX
CASE 506AA
A
L
Y
W
M
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
KT23
ALYWG
G
KLT23
ALYW
G
•
•
•
•
•
•
•
•
3.5 ns Typical Propagation Delay
24 mA TTL Outputs
Flow Through Pinouts
The 100 Series Contains Temperature Compensation
Operating Range V
CC
= 4.75 V to 5.25 V with GND = 0 V
Internal Input 50 KW Pulldown Resistors
Q Output Will Default LOW with Inputs Left Open or < 1.3 V
Pb−Free Packages are Available
1
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
December, 2006
−
Rev. 14
1
Publication Order Number:
MC100ELT23/D
2S MG
G
4
ONSEMI [ ON SEMICONDUCTOR ]
