MC100EP196
3.3V ECL Programmable
Delay Chip with FTUNE
The MC100EP196 is a programmable delay chip (PDC) designed
primarily for clock deskewing and timing adjustment. It provides variable
delay of a differential NECL/PECL input transition. It has similar
architecture to the EP195 with the added feature of further tuneability in
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delay using the FTUNE pin. The FTUNE input takes an analog voltage
from V
CC
to V
EE
to fine tune the output delay from 0 to 60 ps.
MARKING
The delay section consists of a programmable matrix of gates and
DIAGRAM*
multiplexers as shown in the logic diagram, Figure 2. The delay increment
of the EP196 has a digitally selectable resolution of about 10 ps and a net
range of up to 10.2 ns. The required delay is selected by the 10 data select
MC100
inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on
EP196
LEN allows a transparent LOAD mode of real time delay values by
AWLYYWWG
LQFP−32
D[9:0]. A LOW to HIGH transition on LEN will LOCK and HOLD
FA SUFFIX
current values present against any subsequent changes in D[10:0]. The
32
CASE 873A
approximate delay values for varying tap numbers correlating to D0 (LSB)
1
through D9 (MSB) are shown in Table 5.
Because the EP196 is designed using a chain of multiplexers, it has a
fixed minimum delay of 2.4 ns. An additional pin, D10, is provided for
A
= Assembly Location
WL
= Wafer Lot
controlling Pins 14 and 15, CASCADE and CASCADE, also latched
YY
= Year
by LEN, in cascading multiple PDCs for increased programmable
WW
= Work Week
range. The cascade logic allows full control of multiple PDCs.
G
= Pb−Free Package
Switching devices from all “1” states on D[0:9] with SETMAX LOW
to all “0” states on D[0:9] with SETMAX HIGH will increase the
*For additional marking information, refer to
Application Note AND8002/D.
delay equivalent to “D0”, the minimum increment.
Select input pins, D[10:0], may be threshold controlled by
combinations of interconnects between V
EF
(pin 7) and V
CF
(pin 8)
for LVCMOS, ECL, or LVTTL level signals. LVTTL and LVCMOS
ORDERING INFORMATION
operation is available in PECL mode only. For LVCMOS input levels,
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
leave V
CF
and V
EF
open. For ECL operation, short V
CF
and V
EF
(pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply
reference to V
CF
and leave open V
EF
pin. The 1.5 V reference voltage
to V
CF
pin can be accomplished by placing a 2.2 kW resistor between
*For additional information on our Pb−Free strategy
V
CF
and V
EE
for 3.3 V power supply.
and soldering details, please download the
The V
BB
pin, an internally generated voltage supply, is available to
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
this device only. For single−ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The 100 Series contains temperature compensation.
•
Maximum Frequency > 1.2 GHz Typical
•
Open Input Default State
•
Programmable Range: 0 ns to 10 ns
•
Safety Clamp on Inputs
•
Delay Range: 2.4 ns to 12.4 ns
•
A Logic High on the EN Pin Will Force Q to Logic
Low
•
10 ps Increments
•
D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL
•
PECL Mode Operating Range:
Inputs
V
CC
= 3.0 V to 3.6 V with V
EE
= 0 V
•
V
BB
Output Reference Voltage
•
NECL Mode Operating Range:
•
Pb−Free Packages are Available*
V
CC
= 0 V with V
EE
=
−3.0
V to
−3.6
V
©
Semiconductor Components Industries, LLC,2006
November, 2006
−
Rev. 12
1
Publication Order Number:
MC100EP196/D
ONSEMI [ ON SEMICONDUCTOR ]
