MC10EP33, MC100EP33
3.3V / 5V ECL
B4
Divider
Description
The MC10/100EP33 is an integrated
B4
divider. The differential
clock inputs.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The reset pin is asynchronous and is asserted on the rising edge.
Upon powerup, the internal flip−flops will attain a random state; the
reset allows for the synchronization of multiple EP33’s in a system.
The 100 Series contains temperature compensation.
Features
http://onsemi.com
MARKING
DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
1
HEP33
ALYW
G
8
KEP33
ALYW
G
8
1
•
320 ps Propagation Delay
•
Maximum Frequency > 4 GHz Typical
•
PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
•
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
−3.0
V to
−5.5
V
•
Open Input Default State
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
HP33
ALYWG
G
8
KP33
ALYWG
G
1
1
•
•
•
•
5Q MG
G
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at V
EE
V
BB
Output
Pb−Free Packages are Available
DFN8
MN SUFFIX
CASE 506AA
H
K
5Q
3L
= MC10
= MC100
= MC10
= MC100
1
4
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
December, 2006
−
Rev. 9
1
Publication Order Number:
MC10EP33/D
3L MG
G
4
ONSEMI [ ON SEMICONDUCTOR ]
