MC10EP52, MC100EP52
3.3V / 5V ECL Differential
Data and Clock D Flip−Flop
Description
The MC10EP/100EP52 is a differential data, differential clock D
flip−flop. The device is pin and functionally equivalent to the EL52
device.
Data enters the master portion of the flip−flop when the clock is
LOW and is transferred to the slave, and thus the outputs, upon a
positive transition of the clock. The differential clock inputs of the
EP52 allow the device to also be used as a negative edge triggered
device.
The EP52 employs input clamping circuitry so that under open input
conditions (pulled down to V
EE
) the outputs of the device will remain
stable.
The 100 Series contains temperature compensation.
Features
http://onsemi.com
MARKING
DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
1
HEP52
ALYW
G
8
KEP52
ALYW
G
8
1
5T MG
G
DFN8
MN SUFFIX
CASE 506AA
H
K
5T
3O
= MC10
= MC100
= MC10
= MC100
1
4
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
December, 2006
−
Rev. 6
1
Publication Order Number:
MC10EP52/D
3OMG
G
4
•
•
•
•
•
•
•
•
330 ps Typical Propagation Delay
Maximum Frequency
u
4 GHz Typical
PECL Mode: V
CC
= 3.0 V to 5.5 V with V
EE
= 0 V
NECL Mode: V
CC
= 0 V with V
EE
=
−3.0
V to
−5.5
V
Open Input Default State
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at V
EE
Pb−Free Packages are Available
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
HP52
ALYWG
G
8
KP52
ALYWG
G
1
1
ONSEMI [ ON SEMICONDUCTOR ]
