MC100EPT23
3.3V Dual Differential
LVPECL/LVDS/CML to
LVTTL/LVCMOS Translator
The MC100EPT23 is a dual differential LVPECL/LVDS/CML to
LVTTL/LVCMOS translator. Because LVPECL (Positive ECL),
LVDS, and positive CML input levels and LVTTL/LVCMOS output
levels are used, only +3.3 V and ground are required. The small
outline 8-lead SOIC package and the dual gate design of the EPT23
makes it ideal for applications which require the translation of a clock
or data signal.
The EPT23 is available in only the ECL 100K standard. Since there
are no LVPECL outputs or an external V
BB
reference, the EPT23 does
not require both ECL standard versions. The LVPECL/LVDS inputs
are differential. Therefore, the MC100EPT23 can accept any standard
differential LVPECL/LVDS input referenced from a V
CC
of +3.3 V.
Features
http://onsemi.com
MARKING
DIAGRAMS*
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
KPT23
ALYW
G
8
8
1
TSSOP−8
DT SUFFIX
CASE 948R
1
KA23
ALYWG
G
Pb−Free Packages are Available
DFN8
MN SUFFIX
CASE 506AA
1
A
L
Y
W
M
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
December, 2006 − Rev. 15
Publication Order Number:
MC100EPT23/D
3T M
G
G
4
•
•
•
•
•
•
1.5 ns Typical Propagation Delay
Maximum Operating Frequency > 275 MHz
LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs
24 mA LVTTL Outputs
Operating Range: V
CC
= 3.0 V to 3.6 V with GND = 0 V
ONSEMI [ ON SEMICONDUCTOR ]
