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MC10H680FNG 参数 Datasheet PDF下载

MC10H680FNG图片预览
型号: MC10H680FNG
PDF下载: 下载PDF文件 查看货源
内容描述: 4位差分ECL总线为TTL总线收发器 [4−Bit Differential ECL Bus to TTL Bus Transceiver]
分类和应用: 总线收发器转换器电平转换器驱动程序和接口锁存器接口集成电路
文件页数/大小: 10 页 / 138 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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MC10H680, MC100H680
4−Bit Differential ECL Bus
to TTL Bus Transceiver
Description
The MC10H/100H680 is a dual supply 4−bit differential ECL bus to
TTL bus transceiver. It is designed to allow the system designer to no
longer be limited in bus speed associated with standard TTL busses.
Using a differential ECL Bus will increase the frequency of operation
and increase noise immunity.
Both the TTL and the ECL ports are capable of driving a bus. The
ECL outputs have the ability to drive 25
W,
allowing both ends of the
bus line to be terminated in the characteristic impedance of 50
W.
The
TTL outputs are specified to source 15 mA and sink 48 mA, allowing
the ability to drive highly capacitive loads.
The ECL output levels are V
OH
approximately equal to
−1.0
V and
V
OL
cutoff equal to
−2.0
V (VTT). When the ECL ports are disabled
both EIOx and EIOxB go to the V
OL
cutoff level. The ECL input
receivers have special circuitry which detects this disabled condition,
prevents oscillation, and forces the TTL output to the low state. The
noise margin in this disabled state is greater than 600 mV. Multiple
ECL V
CCO
pins are utilized to minimize switching noise.
The TTL ports have standard levels. The TTL input receivers have
PNP input devices to significantly reduce loading. Multiple TTL
power and ground pins are utilized to minimize switching noise.
The control pins (EDIR and ECEB) of the 10H version is
compatible with MECL 10H™ ECL logic levels. The control pins of
the 100H version are compatible with 100K levels.
Features
http://onsemi.com
PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxH680G
AWLYYWW
Differential ECL Bus (25
W)
I/O Ports
High Drive TTL Bus I/O Ports
Extra TTL and ECL Power/Ground Pins to Minimize
Switching Noise
Dual Supply
Direction and Chip Enable Control Pins
Pb−Free Packages are Available*
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
November, 2006
Rev. 11
1
Publication Order Number:
MC10H680/D