MC100LVE310
Q0
25
V
EE
CLK_SEL
CLKa
V
CC
CLKa
V
BB
CLKb
26
27
28
1
2
3
4
5
CLKb
6
NC
7
8
9
Q7
10
Q6
11
Q6
Q0
24
Q1 V
CCO
Q1
23
22
21
Q2
20
Q2
19
18
17
16
Q3
Q3
Q4
V
CCO
Q4
Q5
Q5
CLKa
CLKa
CLKb
CLKb
CLK_SEL
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
V
BB
Pinout: 28−Lead PLCC
(Top View)
15
14
13
12
Q7 V
CCO
Warning: All V
CC
, V
CCO
, and V
EE
pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout Assignment
Table 1. PIN DESCRIPTION
PIN
CLKa, CLKa; ,CLKb CLKb
Q0:7, Q0:7
CLK_SEL
V
BB
V
CC
, V
CCO
V
EE
NC
FUNCTION
ECL Differential Input Clocks
ECL Differential Outputs
ECL Input Clock Select
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
Figure 2. Logic Symbol
Table 2. TRUTH TABLE
CLK_SEL
L
H
Input Clock
CLKa Selected
CLKb Selected
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Pb Pkg
Level 1
Value
YES
N/A
> 2 kV
> 200 V
Pb−Free Pkg
Level 3
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
PLCC−28
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
212 Devices
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