MC100LVE310
3.3V ECL 2:8 Differential
Fanout Buffer
Description
The MC100LVE310 is a low voltage, low skew 2:8 differential ECL
fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and
system skew. The LVE310 offers two selectable clock inputs to allow
for redundant or test clocks to be incorporated into the system clock
trees.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50
W,
even if
only one side is being used. In most applications all eight differential
pairs will be used and therefore terminated. In the case where fewer
than eight pairs are used it is necessary to terminate at least the output
pairs adjacent to the output pair being used in order to maintain
minimum skew. Failure to follow this guideline will result in small
degradations of propagation delay (on the order of 10
−
20 ps) of the
outputs being used, while not catastrophic to most designs this will
result in an increase in skew. Note that the package corners isolate
outputs from one another such that the guideline expressed above
holds only for outputs on the same side of the package.
The MC100LVE310, as with most ECL devices, can be operated
from a positive V
CC
supply in LVPECL mode. This allows the
LVE310 to be used for high performance clock distribution in +3.3 V
systems. Designers can take advantage of the LVE310’s performance
to distribute low skew clocks across the backplane or the board. In a
PECL environment series or Thevenin line terminations are typically
used as they require no additional power supplies, if parallel
termination is desired a terminating voltage of V
CC
−
2.0 V will need
to be provided. For more information on using PECL, designers
should refer to Application Note AN1406/D.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
http://onsemi.com
PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MC100LVE310G
AWLYYWW
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
•
200 ps Part−to−Part Skew
•
50 ps Output−to−Output Skew
•
PECL Mode Operating Range:
•
Q Output will Default LOW with All Inputs Open or
at V
EE
•
The 100 Series Contains Temperature Compensation
•
Pb−Free Packages are Available*
V
CC
= 3.0 V to 3.8 V with V
EE
= 0 V
•
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
=
−3.0
V to
−3.8
V
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
November, 2006
−
Rev. 4
1
Publication Order Number:
MC100LVE310/D
ONSEMI [ ON SEMICONDUCTOR ]
