MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Registered Hex TTL/ECL
Translator
The MC10H/100H604 is a 6–bit, registered, dual supply TTL to ECL
translator. The device features differential ECL outputs as well as a choice
between either a differential ECL clock input or a TTL clock input. The
asynchronous master reset control is an ECL level input..
With its differential ECL outputs and TTL inputs the H604 device is ideally
suited for the transmit function of a HPPI bus type board–to–board interface
application. The on chip registers simplify the task of synchronizing the data
between the two boards.
The device is available in either ECL standard: the 10H device is
compatible with MECL 10KH logic levels while the 100H device is
compatible with 100K logic levels.
•
•
•
•
•
Differential 50Ω ECL Outputs
Choice Between Differential ECL or TTL Clock Input
Dual Power Supply
Multiple Power and Ground Pins to Minimize Noise
Specified Within–Device Skew
MC10H604
MC100H604
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
PIN NAMES
PIN
D0–D5
CLK, CLK
TCLK
MR
Q0–Q5
Q0–Q5
VCCE
VCCT
VEE
FUNCTION
TTL Data Inputs
Differential ECL Clock Input
TTL Clock Input
ECL Master Reset Input
True ECL Outputs
Inverted ECL Outputs
ECL VCC (0V)
TTL VCC (+5.0V)
ECL VEE (–5.2V)
LOGIC SYMBOL
1 OF 6 BITS
Qn
Qn
Dn
D
Q
TRUTH TABLE
Dn
MR
L
L
H
TCLK/CLK
Z
Z
X
Qn+1
L
H
L
CLK
R
L
H
X
Z = LOW to HIGH Transition
CLK
CLK
TCLK
Pinout: 28–Lead PLCC
(Top View)
*
D0
26
27
28
D1 D2 VCCT D3
25
24
23
22
D4
21
D5 VCCE
20
19
18
17
16
15
Q5
Q5
Q4
Q4
VCCE
Q3
Q3
MR
VBB
TCLK
VBB
CLK
CLK
2
3
4
5
6
7
8
9
10
11
14
13
12
*
1. When using MECL inputs, TCLK must be tied to ground (0V).
2. When using only one MECL input, the unused MECL input must be tied
to VBB, and TCLK must be tied to ground (0V).
3. When using TCLK, both MECL inputs must be tied to VEE (–5.2V).
MR
VCCE
Q0 Q0 VEE Q1 Q1 Q2
Q2
9/96
©
Motorola, Inc. 1996
2–302
REV 1
ONSEMI [ ON SEMICONDUCTOR ]
