MC10104
Quad 2-Input AND Gate
The MC10104 is a quad 2–input AND gate. One of the gates has
both AND/NAND outputs available.
•
P
D
= 35 mW typ/gate (No Load)
•
t
pd
= 2.7 ns typ
•
t
r
, t
f
= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
4
5
6
7
10
11
12
13
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
2
3
14
9
15
PDIP–16
P SUFFIX
CASE 648
1
1
PLCC–20
FN SUFFIX
CASE 775
10104
AWLYYWW
CDIP–16
L SUFFIX
CASE 620
1
16
MC10104P
AWLYYWW
http://onsemi.com
MARKING
DIAGRAMS
16
MC10104L
AWLYYWW
DIP
PIN ASSIGNMENT
V
CC1
A
OUT
B
OUT
A
IN
A
IN
B
IN
B
IN
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
D
OUT
C
OUT
D
IN
D
IN
C
IN
C
IN
D
OUT
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
MC10104L
MC10104P
MC10104FN
Package
CDIP–16
PDIP–16
PLCC–20
Shipping
25 Units / Rail
25 Units / Rail
46 Units / Rail
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
©
Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10104/D
ONSEMI [ ON SEMICONDUCTOR ]
