MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Triple 2-3-2-Input OR/NOR
Gate
The MC10105 is a triple 2–3–2 input OR/NOR gate.
MC10105
PD = 30 mW typ/gate (No Load)
tpd = 2.0 ns typ
tr, tf = 2.0 ns typ (20%–80%)
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
LOGIC DIAGRAM
4
5
9
10
11
13
12
3
2
6
7
14
15
DIP
PIN ASSIGNMENT
VCC1
AOUT
AOUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
COUT
COUT
CIN
CIN
BIN
BIN
BIN
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
AIN
AIN
BOUT
BOUT
VEE
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
©
Motorola, Inc. 1996
3–21
REV 5
ONSEMI [ ON SEMICONDUCTOR ]
