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MC10E1652FNG 参数 Datasheet PDF下载

MC10E1652FNG图片预览
型号: MC10E1652FNG
PDF下载: 下载PDF文件 查看货源
内容描述: 5V , -5V ECL双路ECL输出比较器与锁存器 [5V, −5V ECL Dual ECL Output Comparator with Latch]
分类和应用: 锁存器比较器
文件页数/大小: 10 页 / 139 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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MC10E1652
5V, −5V ECL Dual ECL Output
Comparator with Latch
The MC10E1652 is fabricated using ON Semiconductor’s advanced
MOSAIC IIIt process and is output compatible with 10H logic
devices. In addition, the device is available in both a 16-pin DIP and a
20-pin surface mount package. However, the MC10E1652 provides
user programmable hysteresis.
The latch enable (LEN
a
and LEN
b
) input pins operate from standard
ECL 10H logic levels. When the latch enable is at a logic high level,
the MC10E1652 acts as a comparator; hence, Q will be at a logic high
level if V1 > V2 (V1 is more positive than V2). Q is the complement
of Q. When the latch enable input goes to a low logic level, the outputs
are latched in their present state, providing the latch enable setup and
hold time constraints are met. The level of input hysteresis is
controlled by applying a bias voltage to the HYS pin.
Features
http://onsemi.com
MARKING
DIAGRAMS
16
MC10E1652L
AWLYYWW
1
CDIP−16
L SUFFIX
CASE 620A
1 20
Typical 3.0 dB Bandwidth > 1.0 GHz
Typical V to Q Propagation Delay of 775 ps
Typical Output Rise/Fall of 350 ps
Common Mode Range
−2.0
V to +3.0 V
Individual Latch Enables
Differential Outputs
Operating Mode: V
CC
= 5.0 V, V
EE
=
−5.2
V, GND = 0 V
Programmable Input Hysteresis
No Internal Input Pulldown Resistors
20 1
PLCC−20
FN SUFFIX
CASE 775
A
WL
YY
WW
G
MC10E
1652FNG
AWLYYWW
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 100 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−O @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 85 devices
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
1
Publication Order Number:
MC10E1652/D
©
Semiconductor Components Industries, LLC, 2006
November, 2006
Rev. 9