MC10EP05, MC100EP05
3.3V / 5V ECL 2−Input
Differential AND/NAND
The MC10/100EP05 is a 2−input differential AND/NAND gate.
The device is functionally equivalent to the EL05 and LVEL05
devices. With AC performance much faster than the LVEL05 device,
the EP05 is ideal for applications requiring the fastest
AC performance available.
The 100 Series contains temperature compensation.
http://onsemi.com
MARKING DIAGRAMS*
8
8
1
SOIC−8
D SUFFIX
CASE 751
HEP05
ALYW
1
1
8
KEP05
ALYW
•
220 ps Typical Propagation Delay
•
Maximum Frequency > 3 GHz Typical
•
PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
•
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −3.0 V to −5.5 V
•
Open Input Default State
•
Safety Clamp on Inputs
8
8
1
TSSOP−8
DT SUFFIX
CASE 948R
HP05
ALYW
1
8
KP05
ALYW
1
•
Q Output Will Default LOW with Inputs Open or at V
EE
•
Pb−Free Package is Available
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2004
1
June, 2004 − Rev. 6
Publication Order Number:
MC10EP05/D
ONSEMI [ ON SEMICONDUCTOR ]
