MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Registered Hex TTL/PECL
Translator
The MC10/100H606 is a 6–bit, registered, single supply TTL to PECL
translator. The device features differential PECL outputs as well as a choice
between either a differential PECL clock input or a TTL clock input. The
asynchronous master reset control is a PECL level input.
With its differential PECL outputs and TTL inputs the H606 device is
ideally suited for the transmit function of a HPPI bus type board–to–board
interface application. The on chip registers simplify the task of synchronizing
the data between the two boards.
The device is available in either ECL standard: the MECL™ 10H device is
compatible with MECL 10KH logic levels, with a VCC of +5 volts; while the
100H device is compatible with 100K logic levels, with a VCC of +5 volts.
•
•
•
•
Differential 50Ω ECL Outputs
Choice Between Differential PECL or TTL Clock Input
Single Power Supply
Multiple Power and Ground Pins to Minimize Noise
MC10H606
MC100H606
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
PIN NAMES
PIN
FUNCTION
TTL Data Inputs
Differential PECL Clock Input
TTL Clock Input
PECL Master Reset Input
True PECL Outputs
Inverted PECL Outputs
PECL VCC (+5.0V)
TTL VCC (+5.0V)
TTL/PECL Ground
LOGIC SYMBOL
1 OF 6 BITS
Qn
Qn
Dn
D
Q
D0–D5
CLK, CLK
TCLK
MR
Q0–Q5
Q0–Q5
VCCE
VCCT
GND
TRUTH TABLE
Dn
MR
L
L
H
TCLK/CLK
Z
Z
X
Qn+1
L
H
L
CLK
R
L
H
X
Z = LOW to HIGH Transition
CLK
CLK
TCLK
*
Pinout: 28–Lead PLCC
(Top View)
D1 D2 VCCT D3
25
24
23
22
D4
21
D5 VCCE
20
19
18
17
16
15
MR
VBB
D0
TCLK
VBB
CLK
26
27
28
Q5
Q5
Q4
Q4
VCCE
Q3
Q3
*
1. When using PECL inputs, TCLK must be tied to ground (0V).
2. When using only one PECL input, the unused PECL input must be tied
to VBB, and TCLK must be tied to ground (0V).
3. When using TCLK, both PECL inputs must be tied to ground (0V).
CLK
MR
VCCE
2
3
4
5
6
7
8
9
10
11
14
13
12
Q0 Q0 GND Q1 Q1 Q2
Q2
MECL 10H is a trademark of Motorola, Inc.
9/96
©
Motorola, Inc. 1996
2–311
REV 1
ONSEMI [ ON SEMICONDUCTOR ]
