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MC14042BD 参数 Datasheet PDF下载

MC14042BD图片预览
型号: MC14042BD
PDF下载: 下载PDF文件 查看货源
内容描述: 四核透明锁存器 [Quad Transparent Latch]
分类和应用: 触发器锁存器逻辑集成电路光电二极管
文件页数/大小: 8 页 / 178 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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MC14042B
Quad Transparent Latch
The MC14042B Quad Transparent Latch is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Each latch has a separate data input, but all four
latches share a common clock. The clock polarity (high or low) used to
strobe data through the latches can be reversed using the polarity
input. Information present at the data input is transferred to outputs Q
and Q during the clock level which is determined by the polarity input.
When the polarity input is in the logic “0” state, data is transferred
during the low clock level, and when the polarity input is in the logic
“1” state the transfer occurs during the high clock level.
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
MC14042BCP
AWLYYWW
1
16
SOIC–16
D SUFFIX
CASE 751B
1
16
SOEIAJ–16
F SUFFIX
CASE 966
Unit
V
V
mA
mW
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
1
MC14042B
AWLYWW
14042B
AWLYWW
Buffered Data Inputs
Common Clock
Clock Polarity Control
Q and Q Outputs
Double Diode Input Protection
Supply Voltage Range = 3.0 Vdc to 1 8 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 3.)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8–Second Soldering)
Value
– 0.5 to +18.0
– 0.5 to V
DD
+ 0.5
±
10
500
– 55 to +125
– 65 to +150
260
ORDERING INFORMATION
°C
°C
°C
Device
MC14042BCP
MC14042BD
MC14042BDR2
MC14042BF
MC14042BFEL
MC14042BFR1
MC14042BFR2
Package
PDIP–16
SOIC–16
SOIC–16
SOEIAJ–16
SOEIAJ–16
SOEIAJ–16
SOEIAJ–16
Shipping
2000/Box
2400/Box
2500/Tape & Reel
See Note 1.
See Note 1.
See Note 1.
See Note 1.
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
v
v
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
©
Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 3
Publication Order Number:
MC14042B/D