MC14049UB
Hex Buffers
The MC14049UB hex inverter/buffer is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. This complementary MOS device finds primary
use where low power dissipation and/or high noise immunity is
desired. This device provides logic−level conversion using only one
supply voltage, V
DD
. The input−signal high level (V
IH
) can exceed the
V
DD
supply voltage for logic−level conversions. Two TTL/DTL
Loads can be driven when the device is used as CMOS−to−TTL/DTL
converters (V
DD
= 5.0 V, V
OL
v
0.4 V, I
OL
≥
3.2 mA). Note that pins
13 and 16 are not connected internally on this device; consequently
connections to these terminals will not affect circuit operation.
Features
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP−16
P SUFFIX
CASE 648
MC14049UBCP
AWLYYWW
1
16
SOIC−16
D SUFFIX
CASE 751B
1
16
TSSOP−16
DT SUFFIX
CASE 948F
14
049U
ALYW
1
16
SOEIAJ−16
F SUFFIX
CASE 966
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
MC14049UB
ALYW
14049U
AWLYWW
•
•
•
•
•
•
•
High Source and Sink Currents
High−to−Low Level Converter
Supply Voltage Range = 3.0 V to 18 V
Meets JEDEC UB Specifications
V
IN
can exceed V
DD
Improved ESD Protection on All Inputs
Pb−Free Packages are Available*
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
V
out
I
in
I
out
P
D
Parameter
DC Supply Voltage Range
Input Voltage Range
(DC or Transient)
Output Voltage Range
(DC or Transient)
Input Current
(DC or Transient) per Pin
Output Current
(DC or Transient) per Pin
Power Dissipation, per Package (Note 1)
Plastic
SOIC
Ambient Temperature Range
Storage Temperature Range
Lead Temperature (8−Second Soldering)
Value
−0.5 to +18.0
−0.5 to +18.0
−0.5 to V
DD
+0.5
±
10
+45
Unit
V
V
V
mA
mA
mW
825
740
−55 to +125
−65 to +150
260
°C
°C
°C
T
A
T
stg
T
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
1. Temperature Derating: All Packages: See Figure 4.
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields referenced to the V
SS
pin, only. Extra precautions
must be taken to avoid applications of any voltage higher than the maximum rated
voltages to this high−impedance circuit. For proper operation, the ranges V
SS
v
V
in
v
18 V and V
SS
v
V
out
v
V
DD
are recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2004
1
December, 2004 − Rev. 6
Publication Order Number:
MC14049UB/D
ONSEMI [ ON SEMICONDUCTOR ]
