MC14094B
8−Stage Shift/Store Register
with Three−State Outputs
The MC14094B combines an 8−stage shift register with a data latch
for each stage and a 3−state output from each latch.
Data is shifted on the positive clock transition and is shifted from the
seventh stage to two serial outputs. The Q
S
output data is for use in
high−speed cascaded systems. The Q
S
output data is shifted on the
following negative clock transition for use in low−speed cascaded
systems.
Data from each stage of the shift register is latched on the negative
transition of the strobe input. Data propagates through the latch while
strobe is high.
Outputs of the eight data latches are controlled by 3−state buffers
which are placed in the high−impedance state by a logic Low on
Output Enable.
Features
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
16
MC14094BCP
AWLYYWWG
1
16
SOIC−16
D SUFFIX
CASE 751B
1
14094BG
AWLYWW
•
3−State Outputs
•
Capable of Driving Two Low−Power TTL Loads or One Low−Power
•
•
•
•
•
•
Schottky TTL Load Over the Rated Temperature Range
Input Diode Protection
Data Latch
Dual Outputs for Data Out on Both Positive and
Negative Clock Transitions
Useful for Serial−to−Parallel Data Conversion
Pin−for−Pin Compatible with CD4094B
Pb−Free Packages are Available*
16
TSSOP−16
DT SUFFIX
CASE 948F
1
14
094B
ALYW
16
SOEIAJ−16
F SUFFIX
CASE 966
Unit
V
V
mA
mW
°C
°C
°C
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
1
MC14094B
ALYWG
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±
10
500
−55 to +125
−65 to +150
260
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
©
Semiconductor Components Industries, LLC, 2005
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
1
August, 2005 − Rev. 6
Publication Order Number:
MC14094B/D
ONSEMI [ ON SEMICONDUCTOR ]
