MC14572UB
Hex Gate
The MC14572UB hex functional gate is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. These complementary MOS logic gates find
primary use where low power dissipation and/or high noise immunity
is desired. The chip contains four inverters, one NOR gate and one
NAND gate.
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
MC14572UBCP
AWLYYWW
1
16
SOIC–16
D SUFFIX
CASE 751B
1
16
SOEIAJ–16
F SUFFIX
CASE 966
MC14572UB
AWLYWW
1
Unit
V
V
mA
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
14572U
AWLYWW
•
•
•
•
•
Diode Protection on All Inputs
Single Supply Operation
Supply Voltage Range = 3.0 Vdc to 18 Vdc
NOR Input Pin Adjacent to V
SS
Pin to Simplify Use As An Inverter
NAND Input Pin Adjacent to V
DD
Pin to Simplify Use As An
Inverter
•
NOR Output Pin Adjacent to Inverter Input Pin For OR Application
•
NAND Output Pin Adjacent to Inverter Input Pin For AND
Application
•
Capable of Driving Two Low–power TTL Loads or One Low–Power
Schottky TTL Load over the Rated Temperature Range
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 3.)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8–Second Soldering)
Value
– 0.5 to +18.0
– 0.5 to V
DD
+ 0.5
±10
500
– 55 to +125
– 65 to +150
260
ORDERING INFORMATION
mW
°C
°C
°C
Device
MC14572UBCP
MC14572UBD
MC14572UBDR2
MC14572UBF
MC14572UBFEL
Package
PDIP–16
SOIC–16
SOIC–16
SOEIAJ–16
SOEIAJ–16
Shipping
2000/Box
48/Rail
2500/Tape & Reel
See Note 1.
See Note 1.
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
v
v
©
Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 3
Publication Order Number:
MC14572UB/D
ONSEMI [ ON SEMICONDUCTOR ]
