MC14598B
8−Bit Bus−Compatible
Latches
The MC14598B is an 8−bit latch addressed with an external binary
address. The 8 latch−outputs are high drive, three−state and bus line
compatible. The drive capability allows direct applications with MPU
systems such as the Motorola 6800 family.
The latches of the MC14598B are accessed via the Address pins,
A0, A1, and A2.
All 8 outputs from the latches are available in parallel when Enable
is in the low state. Data is entered into a selected latch from the Data
pin when the Strobe is high. Master reset is available on both parts.
Features
http://onsemi.com
PDIP−18
P SUFFIX
CASE 707
1
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Serial Data Input
Three−State Bus Compatible Parallel Outputs
Three−State Control Pin (Enable) TTL Compatible Input
Open Drain Full Flag (Multiple Latch Wire−O Ring)
Master Reset
Level Shifting Inputs on All Except Enable
Diode Protection — All Inputs
Supply Voltage Range — 3.0 Vdc to 18 Vdc
Capable of Driving TTL Over Rated Temperature Range With
Fanout as Follows: 1 TTL Load
4 LSTTL Loads
•
Pb−Free Package is Available*
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Parameter
DC Supply Voltage Range
Input Voltage Range, enable
(DC or Transient)
Input Voltage Range, all Other Inputs
(DC or Transient)
Output Voltage Range, (DC or Transient)
Input or Output Current (DC or Transient)
per Pin
Power Dissipation per Package (Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature (8−Second Soldering)
Symbol
V
DD
V
in
V
in
V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Value
−0.5 to +18.0
−0.5 to V
DD
+0.5
−0.5 to V
DD
+12
−0.5 to V
DD
+0.5
±10
500
−55 to +125
−65 to +150
260
Unit
V
V
V
V
mA
mW
°C
°C
°C
MARKING DIAGRAM
18
MC14598BCP
AWLYYWWG
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
OUTPUT TRUTH TABLE
Enable
1
0
Outputs
High Impedance
D
n
D
n
= State of nth latch
NC = NO CONNECTION
ORDERING INFORMATION
Device
MC14598BCP
MC14598BCPG
Package
PDIP−18
PDIP−18
(Pb−Free)
Shipping
20 Units/Rail
20 Units/Rail
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From
65_C To 125_C
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum
rated voltages to this high−impedance circuit. For
proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
or
V
DD
). Unused outputs must be left open.
Publication Order Number:
MC14598B/D
1
June, 2006 − Rev. 6
ONSEMI [ ON SEMICONDUCTOR ]
