MC74AC377, MC74ACT377
Octal D Flip−Flop with
Clock Enable
The MC74AC377/74ACT377 has eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously, when
the Clock Enable (CE) is LOW. The register is fully edge-triggered.
The state of each D input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-flop’s Q
output. The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
http://onsemi.com
PDIP−20
N SUFFIX
CASE 738
1
•
•
•
•
•
•
•
•
•
•
•
•
Ideal for Addressable Register Applications
Clock Enable for Address and Data Synchronization Applications
Eight Edge-Triggered D Flip-Flops
Buffered Common Clock
Outputs Source/Sink 24 mA
See MC74AC273 for Master Reset Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
ACT377 Has TTL Compatible Inputs
MSL = 1 for all Surface Mount
Chip Complexity: 292 FETs or 73 Gates
Pb−Free Packages are Available
SOIC−20W
DW SUFFIX
CASE 751D
1
TSSOP−20
DT SUFFIX
CASE 948E
1
V
CC
20
O
7
19
D
7
18
D
6
17
O
6
16
O
5
15
D
5
14
D
4
13
O
4
12
CP
11
1
SOEIAJ−20
M SUFFIX
CASE 967
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
1
CE
2
O
0
3
D
0
4
D
1
5
O
1
6
O
2
7
D
2
8
D
3
9
O
3
10
GND
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 7 of this data sheet.
Figure 1. Pinout: 20−Lead Packages Conductors
(Top View)
PIN NAMES
PIN
D
0
−D
7
CE
Q
0
−Q
7
CP
FUNCTION
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP
CE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Figure 2. Logic Symbol
©
Semiconductor Components Industries, LLC, 2006
1
December, 2006 − Rev. 9
Publication Order Number:
MC74AC377/D
ONSEMI [ ON SEMICONDUCTOR ]
