MC74HCT125A
Quad 3-State Noninverting
Buffer with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT125A is identical in pinout to the LS125. The device
inputs are compatible with standard CMOS and LSTTL outputs.
The MC74HCT125A noninverting buffer is designed to be used
with 3−state memory address drivers, clock drivers, and other
bus−oriented systems. The devices have four separate output enables
that are active−low.
Features
14
1
http://onsemi.com
MARKING
DIAGRAMS
14
PDIP−14
N SUFFIX
CASE 646
1
MC74HCT125AN
AWLYYWWG
•
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7A Requirements
Chip Complexity: 72 FETs or 18 Equivalent Gates
These are Pb−Free Devices
PIN ASSIGNMENT
LOGIC DIAGRAM
Active−Low Output Enables
A1
OE1
A2
OE2
A3
2
1
5
4
9
10
12
13
PIN 14 = V
CC
PIN 7 = GND
11
Y4
8
Y3
6
Y2
3
Y1
14
14
1
SOIC−14
D SUFFIX
CASE 751A
1
HCT125AG
AWLYWW
14
14
1
TSSOP−14
DT SUFFIX
CASE 948G
1
HCT
125A
ALYWG
G
OE1
A1
Y1
OE2
A2
Y2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
OE4
A4
Y4
OE3
A3
Y3
14
SOEIAJ−14
F SUFFIX
CASE 965
1
A
=
Assembly Location
L, WL
=
Wafer Lot
Y, YY
=
Year
W, WW =
Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
74HCT125A
ALYWG
14
1
FUNCTION TABLE
HCT125A
Inputs
A
H
L
X
OE
L
L
H
Output
Y
H
L
Z
OE3
A4
OE4
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
November, 2009
−
Rev. 1
1
Publication Order Number:
MC74HCT125A/D
ONSEMI [ ON SEMICONDUCTOR ]
