MC74LCX16244
Low−Voltage CMOS
16−Bit Buffer
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
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The MC74LCX16244 is a high performance, non−inverting 16−bit
buffer operating from a 2.3 to 3.6 V supply. The device is nibble
controlled. Each nibble has separate Output Enable inputs which can
be tied together for full 16−bit operation. High impedance TTL
compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A V
I
specification of 5.5 V allows MC74LCX16244
inputs to be safely driven from 5.0 V devices. The MC74LCX16244 is
suitable for memory address driving and all TTL level bus oriented
transceiver applications.
The 4.5 ns maximum propagation delays support high performance
applications. Current drive capability is 24 mA at the outputs. The
Output Enable (OEn) inputs, when HIGH, disable the outputs by
placing them in a HIGH Z condition.
The MC74LCX16244 contains sixteen non−inverting buffers with
3−state 5.0 V−tolerant outputs. The device is nibble controlled with
each nibble functioning identically, but independently. The control
pins may be tied together to obtain full 16−bit operation. The 3−state
outputs are controlled by an Output Enable (OEn) input for each
nibble. When OEn is LOW, the outputs are on. When OEn is HIGH,
the outputs are in the high impedance state.
Features
48
1
TSSOP−48
DT SUFFIX
CASE 1201
MARKING DIAGRAM
48
LCX16244G
AWLYYWW
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Designed for 2.3 V to 3.6 V V
CC
Operation
4.5 ns Maximum t
pd
5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic
Supports Live Insertion and Withdrawal
I
OFF
Specification Guarantees High Impedance When V
CC
= 0 V
LVTTL Compatible
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (20
mA)
Substantially Reduces System Power Requirements
•
Latchup Performance Exceeds 500 mA
•
ESD Performance: Human Body Model >2000 V;
Machine Model >200 V
•
These are Pb−Free Devices*
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2005
1
August, 2005 − Rev. 6
Publication Order Number:
MC74LCX16244/D
ONSEMI [ ON SEMICONDUCTOR ]
