MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad Bus Buffer
With 5V-Tolerant Inputs
The MC74LVX125 is an advanced high speed CMOS quad bus buffer.
The inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
The MC74LVX125 requires the 3–state control input (OE) to be set
High to place the output into the high impedance state.
MC74LVX125
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High Speed: tPD = 4.4ns (Typ) at VCC = 3.3V
Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Low Noise: VOLP = 0.5V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
VCC
14
OE3
13
D3
12
O3
11
OE2
10
D2
9
O2
8
LOW–VOLTAGE CMOS
LVX
D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
DT SUFFIX
14–LEAD TSSOP PACKAGE
CASE 948G–01
1
OE0
2
D0
3
O0
4
OE1
5
D1
6
O1
7
GND
M SUFFIX
14–LEAD SOIC EIAJ PACKAGE
CASE 965–01
Figure 1. 14–Lead Pinout
(Top View)
OE0
D0
OE1
D1
1
2
4
5
6
O1
3
O0
OE2
D2
OE3
D3
10
9
13
12
11
O3
8
O2
PIN NAMES
Pins
OEn
Dn
On
Function
Output Enable Inputs
Data Inputs
3–State Outputs
FUNCTION TABLE
Figure 2. Logic Diagram
OEn
L
L
H
INPUTS
Dn
L
H
X
OUTPUTS
On
L
H
Z
H = High Voltage Level; L = Low Voltage Level; Z = High Imped-
ance State; X = High or Low Voltage Level and Transitions Are
Acceptable, for ICC reasons, DO NOT FLOAT Inputs
6/97
©
Motorola, Inc. 1997
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