MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal Bus Buffer/Line Driver
Inverting with 3-State Outputs
The MC74VHCT240A is an advanced high speed CMOS octal bus buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHCT240A is an inverting 3–state buffer, and has two
active–low output enables. This device is designed to be used with 3–state
memory address drivers, etc.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS
level output swings.
The VHCT240A input and output (when disabled) structures provide
protection when voltages between 0V and 5.5V are applied, regardless of
the supply voltage. These input and output structures help prevent device
destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
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High Speed: tPD = 5.6ns (Typ) at VCC = 5V
Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Designed for 4.5V to 5.5V Operating Range
Low Noise: VOLP = 1.1V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 110 FETs or 27.5 Equivalent Gates
LOGIC DIAGRAM
A1
A2
A3
A4
DATA
INPUTS
B1
B2
B3
B4
2
4
6
8
11
13
15
17
18
16
14
12
9
7
5
3
MC74VHCT240A
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
ORDERING INFORMATION
MC74VHCTXXXADW SOIC
MC74VHCTXXXADT
TSSOP
MC74VHCTXXXAM
SOIC EIAJ
PIN ASSIGNMENT
YA1
OEA
YA2
YA3
YA4
YB1
YB2
YB3
YB4
INVERTING
OUTPUTS
A1
YB4
A2
YB3
A3
YB2
A4
YB1
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
OEB
YA1
B4
YA2
B3
YA3
B2
YA4
B1
FUNCTION TABLE
INPUTS
OUTPUTS
A, B
L
H
X
YA, YB
H
L
Z
OUTPUT
ENABLES
1
OEA
19
OEB
OEA, OEB
L
L
H
6/97
©
Motorola, Inc. 1997
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