NBSG53A
2.5V/3.3V SiGe Selectable
Differential Clock and Data
D Flip−Flop/Clock Divider
with Reset and OLS*
The NBSG53A is a multi−function differential D flip−flop (DFF) or
fixed divide by two (DIV/2) clock generator. This is a part of the
GigaComm™ family of high performance Silicon Germanium
products. A strappable control pin is provided to select between the
two functions. The device is housed in a low profile 4x4 mm 16−pin
Flip−Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package.
The NBSG53A is a device with data, clock, OLS, reset, and select
inputs. Differential inputs incorporate internal 50
W
termination
resistors and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to
program the peak−to−peak output amplitude between 0 and 800 mV
in five discrete steps. The RESET and SELECT inputs are
single−ended and can be driven with either LVECL or
LVCMOS/LVTTL input levels.
Data is transferred to the outputs on the positive edge of the clock.
The differential clock inputs of the NBSG53A allow the device to also
be used as a negative edge triggered device.
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MARKING
DIAGRAM**
SG
53A
LYW
FCBGA−16
BA SUFFIX
CASE 489
QFN−16
MN SUFFIX
CASE 485G
SG53A
ALYW
•
Maximum Input Clock Frequency (DFF) > 8 GHz Typical
(See Figures 4, 6, 8, 10, and 11)
•
Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical
(See Figures 5, 7, 9, 10, and 11)
•
210 ps Typical Propagation Delay (OLS = FLOAT)
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
**For further details, refer to Application
Note AND8002/D
•
•
•
•
45 ps Typical Rise and Fall Times (OLS = FLOAT)
DIV/2 Mode (Active with Select Low)
DFF Mode (Active with Select High)
Board
NBSG53ABAEVB
Description
NBSG53ABA Evaluation Board
Selectable Swing PECL Output with Operating Range: V
CC
= 2.375 V
to 3.465 V with V
EE
= 0 V
•
Selectable Swing NECL Output with NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= −2.375 V to −3.465 V
•
Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV
Peak−to−Peak Output)
•
50
W
Internal Input Termination Resistors on all Differential Inputs
*Output Level Select
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
©
Semiconductor Components Industries, LLC, 2004
1
March, 2004 − Rev. 5
Publication Order Number:
NBSG53A/D
ONSEMI [ ON SEMICONDUCTOR ]
