NCP1203
Power P1
Power P2
Power P3
Figure 17. Output Pulses at Various Power Levels (X = 5.0
ms/div)
P1
t
P2
t
P3
300 M
MAX PEAK
CURRENT
200 M
SKIP CYCLE
CURRENT LIMIT
100 M
0
315.40
882.70
1.450 M
2.017 M
2.585 M
Figure 18. The Skip Cycle Takes Place at Low Peak Currents which Guaranties Noise−Free Operation
We recommend a pin 1 operation between 400 mV and
1.3 V that will fix the skip peak current level between
120 mV/Rsense and 390 mV/Rsense.
Non−Latching Shutdown
In some cases, it might be desirable to shut off the part
temporarily and authorize its restart once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB below the Adj pin 1 level, the
output pulses are disabled as long as FB is pulled below
pin 1. As soon as FB is relaxed, the IC resumes its operation.
Figure 19 depicts the application example.
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