NCV8502 Series
CIRCUIT DESCRIPTION
REGULATOR CONTROL FUNCTIONS
The NCV8502 contains the microprocessor compatible
control function RESET (Figure 12).
1. During Power Up (once the regulation threshold
has been verified).
2. After a reset event has occurred and the device is
back in regulation. The DELAY capacitor is
discharged when the regulation (RESET threshold)
has been violated. This is a latched incident. The
capacitor will fully discharge and wait for the
device to regulate before going through the delay
time event again.
FLAG/Monitor Function
V
IN
RESET
Threshold
DELAY
Threshold
(V
DT
)
V
OUT
DELAY
RESET
T
d
T
d
Figure 12. Reset and Delay Circuit Wave Forms
RESET Function
A RESET signal (low voltage) is generated as the IC
powers up until V
OUT
is within 6.0% of the regulated output
voltage, or when V
OUT
drops out of regulation,and is lower
than 8.0% below the regulated output voltage. Hysteresis is
included in the function to minimize oscillations.
The RESET output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC thereby
guaranteeing that the RESET signal is valid for V
OUT
as low
as 1.0 V.
Adjustable Reset Function
An on−chip comparator is provided to perform an early
warning to the microprocessor of a possible reset signal. The
reset signal typically turns the microprocessor off
instantaneously. This can cause unpredictable results with
the microprocessor. The signal received from the FLAG pin
will allow the microprocessor time to complete its present
task before shutting down. This function is performed by a
comparator referenced to the bandgap reference. The actual
trip point can be programmed externally using a resistor
divider to the input monitor (MON) (Figure 14). The typical
threshold is 1.20 V on the MON pin.
V
BAT
V
IN
V
OUT
NCV8502
MON
R
ADJ
FLAG
C
OUT
I/O
V
CC
mP
RESET
RESET
The reset threshold can be made lower by connecting an
external resistor divider to the R
ADJ
lead from the V
OUT
lead, as displayed in Figure 13. This lead is grounded to
select the default value of 4.6 V.
to
mP
and
System
Power
DELAY GND
Figure 14. FLAG/Monitor Function
Voltage Adjust
R
ADJ
V
OUT
NCV8502
R
RST
C
OUT
Figure 15 shows the device setup for a user configurable
output voltage. The feedback to the V
ADJ
pin is taken from
a voltage divider referenced to the output voltage. The loop
is balanced around the Unity Gain threshold (1.28 V
typical).
V
OUT
NCV8502
V
ADJ
15 k
1.28 V
5.1 k
≈5.0
V
C
OUT
DELAY
RESET
to
mP
and
RESET
Port
C
DELAY
Figure 13. Adjustable RESET
DELAY Function
The reset delay circuit provides a programmable (by
external capacitor) delay on the RESET output lead.
The DELAY lead provides source current (typically 2.5
mA)
to the external DELAY capacitor during the following
proceedings:
Figure 15. Adjustable Output Voltage
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