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SG3526N 参数 Datasheet PDF下载

SG3526N图片预览
型号: SG3526N
PDF下载: 下载PDF文件 查看货源
内容描述: 脉冲宽度调制控制电路 [Pulse Width Modulation Control Circuit]
分类和应用: 稳压器开关式稳压器或控制器电源电路开关式控制器脉冲光电二极管
文件页数/大小: 9 页 / 268 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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SG3526
Pulse Width Modulation
Control Circuit
The SG3526 is a high performance pulse width modulator
integrated circuit intended for fixed frequency switching regulators
and other power control applications.
Functions included in this IC are a temperature compensated
voltage reference, sawtooth oscillator, error amplifier, pulse width
modulator, pulse metering and steering logic, and two high current
totem pole outputs ideally suited for driving the capacitance of power
FETs at high speeds.
Additional protective features include soft start and undervoltage
lockout, digital current limiting, double pulse inhibit, adjustable dead
time and a data latch for single pulse metering. All digital control ports
are TTL and B−series CMOS compatible. Active low logic design
allows easy wired−OR connections for maximum flexibility. The
versatility of this device enables implementation in single−ended or
push−pull switching regulators that are transformerless or transformer
coupled. The SG3526 is specified over a junction temperature range of
0° to +125°C.
8.0 V to 35 V Operation
5.0 V
±1%
Trimmed Reference
1.0 Hz to 400 kHz Oscillator Range
Dual Source/Sink Current Outputs:
±100
mA
Digital Current Limiting
Programmable Dead Time
Undervoltage Lockout
Single Pulse Metering
Programmable Soft−Start
Wide Current Limit Common Mode Range
Guaranteed 6 Unit Synchronization
V
ref
V
CC
Ground
Sync
R
Deadtime
R
T
C
T
Reset
C
Soft−Start
18
17 Reference
Regulator
15
12
11
9 Oscillator
10
5
4
3
V
CC
+
+
SQ
R
Q
Under−
Voltage
Lockout
To Internal
Circuitry
14
V
C
13
Output
A
Soft
Start
Memory
F/F
S
RQ
Toggle
F/F
Q
T
Q
16
Output
B
http://onsemi.com
MARKING
DIAGRAM
18
PDIP−18
N SUFFIX
CASE 707
1
A
WL
YY
WW
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
SG3526N
AWLYYWW
18
PIN CONNECTIONS
+Error
−Error
Compensation
C
Soft−Start
Reset
−CS
+CS
Shutdown
R
T
1
2
3
4
5
6
7
8
9
(Top View)
18 V
ref
17 V
CC
16 Output B
15 Ground
14 V
C
13 Output A
12 Sync
11 R
Deadtime
10 C
T
ORDERING INFORMATION
Device
SG3526N
Package
PDIP−18
Shipping
20 Units/Rail
Compensation
+Error
−Error
+C.S.
−C.S.
Shutdown
1
2
Amp
100 mV
7
+
6
8
Metering
F/F
Figure 1. Representative Block Diagram
©
Semiconductor Components Industries, LLC, 2006
July, 2006
Rev. 4
1
Publication Order Number:
SG3526/D