UC3842B, 43B UC2842B, 43B
Figure 17. Representative Block Diagram
VCC
Vin
VCC
7(12)
36V
Vref
8(14)
RT
2.5V
R
R
Internal
Bias
3.6V
Oscillator
CT
4(7)
+ 1.0mA
Reference
Regulator
VCC
UVLO
+
–
Vref
UVLO
+
–
(See
Text)
VC
7(11)
Output
6(10)
Q1
S
Voltage
Feedback
Input 2(3)
Output/
Compensation 1(1)
2R
R
Error
Amplifier
R
1.0V
Current Sense
Comparator
Gnd
5(9)
Q
PWM
Latch
Power Ground
5(8)
Current Sense Input
3(5)
RS
Pin numbers adjacent to terminals are for the 8–pin dual–in–line package.
Pin numbers in parenthesis are for the D suffix SO–14 package.
= Sink Only Positive True Logic
Figure 18. Timing Diagram
Capacitor CT
Latch
“Set” Input
Output/
Compensation
Current Sense
Input
Latch
“Reset” Input
Output
Large RT/Small CT
Small RT/Large CT
MOTOROLA ANALOG IC DEVICE DATA
9
ONSEMI [ ON SEMICONDUCTOR ]
