Philips Semiconductors
Product specification
Advanced modem/audio analog front-end
UCB1200
The audio sample rate (f
sa
) is derived from the SIB interface clock pin (SIBCLK) and is programmable through the SIB
interface using AUD_DIV[n]. The audio sample rate is given by the following equation:
(
2
×
f
SIBCLK
)
f
sa
=
-------------------------------------------------
-
(
64
×
AUD_DIV[n]
)
(8 < AUD_DIV[n] < 128)
For example, a serial clock of 9.216 MHz, with a divisor of 12, results in an audio sample rate of 24.0 kHz. Both the rising
and the falling edges of SIBCLK are used in case AUD_DIV[n] is set to an odd number, which demands a 50% duty cycle
of SIBCLK to obtain time equidistant sampling.
PASSIVE
V
DDA1
1
7
MICP
21
UCB1200
V
DDA1
1
7
MICP
21
ACTIVE
UCB1200
MICGND
20
V
SSA1
18
MICGND
20
V
SSA1
18
Fig.4 Possible microphone connections.
The UCB1200 audio codec input path accepts microphone signals directly, only a DC blocking capacitor is needed since
the MICP input is biased around 1.4V. The ‘ground’ side of the microphone is either connected to the analog ground
(V
ssa1
) or to the MICGND pin. The latter will decrease the current consumption of active microphones, since the MICGND
pin is made Hi-Z when the audio codec input path is disabled.
The full scale input voltage of the audio input path is programmable in 1.5 dB steps by setting the appropriate number in
AUDIO_GAIN[n] in the audio control register A.
A clip detection circuit will inform the user whenever the input voltage exceeds the maximum input voltage, since this will
lead to a high distortion. In that case AUD_CLIP_STAT in the audio control register B is set. When ACLIP_RIS_INT is
set, an interrupt is generated on the IRQOUT pin on the rising edge of the clip detect signal. When ACLIP_FAL_INT is
set, an interrupt is generated on the falling edge of the clip detect signal.
The frequency response of the audio codec depends mainly on the selected sample rate, since the bandwidth is limited
in the down and up sampling filters. These digital filters both contain several FIR and IIR low pass filters and a DC
removal filter (high pass filter). A 3rd order smoothing filter is implemented in the DAC path, between DAC and speaker
driver stage to reduce the spurious frequencies at the speaker outputs.
1998 Jul 22
8
PHILIPS [ NXP SEMICONDUCTORS ]
