TNY264/266-268
TinySwitch-II
Functional Description
TinySwitch-II
combines a high voltage power MOSFET switch
with a power supply controller in one device. Unlike conventional
PWM (Pulse Width Modulator) controllers,
TinySwitch-II
uses
a simple ON/OFF control to regulate the output voltage.
The
TinySwitch-II
controller consists of an Oscillator, Enable
Circuit (Sense and Logic), Current Limit State Machine, 5.8 V
Regulator, Bypass pin Under-Voltage Circuit, Over
Temperature Protection, Current Limit Circuit, Leading Edge
Blanking and a 700 V power MOSFET.
TinySwitch-II
incorporates additional circuitry for Line Under-Voltage Sense,
Auto-Restart and Frequency Jitter. Figure 2 shows the functional
block diagram with the most important features.
Oscillator
The typical oscillator frequency is internally set to an average
of 132 kHz. Two signals are generated from the oscillator: the
Maximum Duty Cycle signal (DC
MAX
) and the Clock signal that
indicates the beginning of each cycle.
The
TinySwitch-II
oscillator incorporates circuitry that
introduces a small amount of frequency jitter, typically 8 kHz
peak-to-peak, to minimize EMI emission. The modulation rate
of the frequency jitter is set to 1 kHz to optimize EMI reduction
for both average and quasi-peak emissions. The frequency jitter
should be measured with the oscilloscope triggered at the
falling edge of the DRAIN waveform. The waveform in Figure4
illustrates the frequency jitter of the
TinySwitch-II.
Enable Input and Current Limit State Machine
The enable input circuit at the EN/UV pin consists of a low
impedance source follower output set at 1.0 V. The current
through the source follower is limited to 240
µA.
When the
current out of this pin exceeds 240
µA,
a low logic level
PI-2741-041901
(disable) is generated at the output of the enable circuit. This
enable circuit output is sampled at the beginning of each cycle
on the rising edge of the clock signal. If high, the power
MOSFET is turned on for that cycle (enabled). If low, the power
MOSFET remains off (disabled). Since the sampling is done
only at the beginning of each cycle, subsequent changes in the
EN/UV pin voltage or current during the remainder of the cycle
are ignored.
The Current Limit State Machine reduces the current limit by
discrete amounts at light loads when
TinySwitch-II
is likely to
switch in the audible frequency range. The lower current limit
raises the effective switching frequency above the audio range
and reduces the transformer flux density including the associated
audible noise. The state machine monitors the sequence of
EN/UV pin voltage levels to determine the load condition and
adjusts the current limit level accordingly in discrete amounts.
Under most operating conditions (except when close to no-
load), the low impedance of the source follower keeps the
voltage on the EN/UV pin from going much below 1.0 V in the
disabled state. This improves the response time of the optocoupler
that is usually connected to this pin.
5.8 V Regulator and 6.3 V Shunt Voltage Clamp
The 5.8 V regulator charges the bypass capacitor connected to
the BYPASS pin to 5.8 V by drawing a current from the voltage
on the DRAIN pin, whenever the MOSFET is off. The
BYPASS pin is the internal supply voltage node for the
TinySwitch-II.
When the MOSFET is on, the
TinySwitch-II
operates from the energy stored in the bypass capacitor.
Extremely low power consumption of the internal circuitry
allows
TinySwitch-II
to operate continuously from current it
takes from the DRAIN pin. A bypass capacitor value of 0.1
µF
is sufficient for both high frequency decoupling and energy
storage.
In addition, there is a 6.3 V shunt regulator clamping the
BYPASS pin at 6.3 V when current is provided to the BYPASS
pin through an external resistor. This facilitates powering of
TinySwitch-II
externally through a bias winding to decrease the
no load consumption to about 50 mW.
BYPASS Pin Under-Voltage
The BYPASS pin under-voltage circuitry disables the power
MOSFET when the BYPASS pin voltage drops below 4.8 V.
Once the BYPASS pin voltage drops below 4.8 V, it must rise
back to 5.8 V to enable (turn-on) the power MOSFET.
600
500
400
300
200
100
0
136 kHz
128 kHz
V
DRAIN
0
5
10
Time (µs)
Figure 4. Frequency Jitter.
B
7/01
3
POWERINT [ POWER INTEGRATIONS, INC. ]
