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URL: http://www.princeton.com.tw
VFD Driver/Controller IC
When stopped with CL at the high level.
CE
PT6332
CL
DI
0
B0
1
B1
1
B2
1
B3
0
A0
0
A1
0
A2
1
A3
D1
D2
D 56
D 57
C0
0
0
0
0
P1
P2
P3
P4
S0
S1
D M0 D M1 D M2 D M3 D M4 D M5 D M6 D M7 D M8 D M9
0
0
A d d re ss
CE
Di sp l a y D at a
Co n tr o l Da ta
DD
0
B0
1
B1
1
B2
1
B3
0
A0
0
A1
0
A2
1
A3
D 58
D 59
D 11 3 D 11 4
0
0
0
0
0
0
0
0
0
C1
C2
0
0
0
0
0
0
0
0
0
0
0
1
A d d re ss
Di sp l a y D at a
DD
0
B0
1
B1
1
B2
1
B3
0
A0
0
A1
0
A2
1
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
A d d re s s
5 6 b its
DD
Figure 4
Notes:
1. DD
2. Address
3. D1 to D57
4. D58 to D114
5. D53 to D56
6. C0 to C2
: Direction Data
: Applications must send the value (8E
H
) as shown in figure 3 & 4
: Segment display data for the GR1 digit output pin (when P1 ~ P4 = 0)
Dn (n=1 to 57) = 1: Segment on
Dn (n=1 to 57) = 0: Segment off
: Segment display data for the GR2 digit output pin
Dn (n=58 to 114) = 1: Segment on
Dn (n=58 to 114) = 0: Segment off
: General purpose output pin (when P1 ~ P4=1)
Dn (n=53 to 56) = 1: General purpose on (High level)
Dn (n=53 to 56) = 0: General purpose off (Low level)
: Sleep Mode Current Setup
Cn (n=0 to 2)=0: I
DD1
≤
100
µ
A (Normal mode)
Cn (n=0 to 2)=1: I
DD1
≤
5
µ
A (Test mode)
PT6332 V1.0
-9-
February, 2006
PTC [ PRINCETON TECHNOLOGY CORP ]
