October 2006
rev 1.6
Pin Configuration
XIN / CLKIN
XOUT
FS1
LF
1
2
8
7
VDD
FS0
ModOUT
VSS
P2781/82/84
P278xA
3
4
6
5
Standard pin Configuration offered in both
8 pin SOIC and TSSOP Packages
Pin Description (P278xA)
Pin#
1
2
3
4
5
6
7
8
Pin Name
XIN/CLKIN
XOUT
FS1
LF
VSS
ModOUT
FS0
VDD
Type
I
O
I
I
I
O
I
P
Description
Connect to crystal or clock input. This pin has dual functions. It can be connected
either to an external crystal or an external reference clock.
Crystal connection. If using an external reference, this pin must be left
unconnected.
Digital logic input used to select input frequency range
(see the Input Frequency Selection Table). This pin has an internal pull-up
resistor.
External Loop Filter for the PLL. By changing the value of the CRC circuit, the
percentage spread can be adjusted accordingly. See the Loop Filter Selection
Table for detail value.
Ground Connection. Connect to system ground.
Spread Spectrum Clock Output.
Digital logic input used to select input frequency range
(see the Input Frequency Selection Table). This pin has an internal pull-up
resistor.
Connect to +3.3 V
Input Frequency Selection Table
FS1
0
0
1
1
FS0
0
1
0
1
Input (MHz)
3 to 9
10 to 19
20 to 38
39 to 78
Output Frequency Scaling (MHz)
P2781A
3 to 9
10 to 19
20 to 38
39 to 78
P2782A
6 to 18
20 to 38
40 to 76
78 to 156
P2784A
12 to 36
40 to 76
80 to 152
156 to 312
Modulation Rate (KHz)
Fin / 128
Fin / 256
Fin / 512
Fin / 1024
General Purpose EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
