July 2003
Advance Information
PulseC re
AS80SSTVF16857
DDR 14-Bit Registered Buffer
Features
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Differential clock signals
Meets SSTL_2 class II specifications on outputs
Supports SSTL_2 Class I and II specifications
Low voltage operation – V
DD
= 2.3V to 2.7V
Available in 48-pin TSSOP and TVSOP package
Operates at 2.3V to 2.7V for PC1600, PC2100, and
PC2700; 2.5V to 2.7V for PC3200
Pinout and Functionality Compatible with JEDEC
Standard SSTV16857
Recommended Applications
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DDR memory modules
Provides complete DDR DIMM logic solution
with PCV857
SSTL_2-compatible data registers
Block Diagram
Pin Configuration
CLK
CLKB
RESETB
D1
VREF
38
39
34
48
35
R
CLK
D1
Q1
To 13 other channels
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLKB
CLK
VDD
GND
VREF
RESETB
D8
D9
D10
D11
D12
VDD
GND
D13
D14
4.40 mm body, 0.40 mm pitch = TSSOP (TVSOP)
6.10 mm body, 0.50 mm pitch = TSSOP
48-Pin TSSOP & TVSOP
8/1/03; V.0.10
Alliance Semiconductor
AS80SSTVF16857
P. 1 of 12
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