January 2006
rev 0.2
2.5V CMOS 1-TO-10 CLOCK DRIVER
Features
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High frequency > 150MHz
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Guaranteed low skew < 150pS (max.) between any
two outputs
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Very low duty cycle distortion < 300pS
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High speed: propagation delay < 3nS
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Very low CMOS power levels
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TTL compatible inputs and outputs
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1:10 fanout
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Maximum output rise and fall time < 1.25nS (max.)
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Low input capacitance: 3pF (typ)
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2.5V Supply Voltage
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Available in SSOP and QSOP Packages
ASM2P20807A
Product Description
The ASM2P20807A is a 2.5V compatible, high speed, low
noise, 1:10 fanout, non-inverting clock buffer. The large
fanout from a single input reduces loading on the preceding
driver and provides an efficient clock distribution network.
Providing output to output skew as low as 150pS, the
ASM20807A is an ideal clock distribution device for
synchronous systems. Multiple power and grounds reduce
noise. Typical applications are clock and signal distribution.
Block Diagram
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IN
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Alliance Semiconductor
2575 Augustine Drive
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Santa Clara, CA
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Tel: 408.855.4900
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Fax: 408.855.4999
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www.alsc.com
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
