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ASM2I2310AF-24TT 参数 Datasheet PDF下载

ASM2I2310AF-24TT图片预览
型号: ASM2I2310AF-24TT
PDF下载: 下载PDF文件 查看货源
内容描述: 2.5 V至3.3 V高性能时钟缓冲器 [2.5-V TO 3.3-V High-Performance Clock Buffer]
分类和应用: 时钟驱动器逻辑集成电路光电二极管ISM频段
文件页数/大小: 11 页 / 457 K
品牌: PULSECORE [ PulseCore Semiconductor ]
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November 2006
rev 0.3
2.5-V TO 3.3-V High-Performance Clock Buffer
Features
High-Performance 1:10 Clock Driver for General Purpose
applications. Operates up to 200 MHz at 3.3V Supply
Voltage
Pin-to-Pin Skew < 100 pS at 3.3V Supply Voltage
Supply Range : 2.3V to 3.6V
Operating Temperature Range : -40°C to 85°C
Output Enable Glitch Suppression
Distributes One Clock Input to Two Banks of Five
Outputs
25Ω On Chip Series Damping Resistors
Packaged in 24 Pin TSSOP Package
ASM2P2310A
Product Description
The ASM2P2310A is a high-performance, low-skew clock
buffer that operates up to 200MHz. Two banks of five
outputs each provide low-skew copies of CLK. After power
up, the default state of the outputs is low regardless of the
state of the control pins. For normal operation, the outputs
of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state
when the control pins (1G or 2G, respectively) are held low
and a negative clock edge is detected on the CLK input.
The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into
the buffer mode when the control pins (1G and 2G) are
held high and a negative clock edge is detected on the CLK
input. The device operates in a 2.5V and 3.3V environment.
The built-in output enable glitch suppression ensures a
synchronized output enable sequence to distribute full
period clock signals.
The ASM2P2310A is characterized for operation from
-40°C to 85°C.
Block Diagram
CLK
24
3
25Ω
1Y0
21
25Ω
2Y0
4
25Ω
1Y1
20
25Ω
2Y1
5
25Ω
1Y2
17
25Ω
2Y2
8
25Ω
1Y3
16
25Ω
2Y3
9
1G
11
25Ω
LOGIC CONTROL
1Y4
2G
13
LOGIC CONTROL
12
25Ω
2Y4
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.