November 2006
rev 0.3
ASM2P3807A
Enable and Disable Time
Switch Position
Test
Switch
Disable LOW
6V
Enable LOW
Disable HIGH
Enable HIGH
GND
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Waveforms
3V
1.5V
INPUT
OV
tPLH
tPHL
VOH
2.0 V
1.5 V
0.8 V
OUTPUT
VOL
tR
tF
Package Delay
1.5V
OV
INPUT
tPLH
tPLH
VOH
1.5 V
VOL
3V
OUTPUT
tSK(p) =[ tPHL – tPLH
]
Pulse Skew - tSK(P)
3.3V CMOS 1-TO-10 CLOCK DRIVER
11 of 18
Notice: The information in this document is subject to change without notice.