November 2006
rev 0.2
Power Supply Characteristics for HSTL Outputs
1
Symbol
I
DDQ
I
DDQQ
I
DDD
I
DDDQ
ASM2P5T905A
Parameter
Quiescent V
DD
Power Supply
Current
Quiescent V
DDQ
Power Supply
Current
Dynamic V
DD
Power Supply
Current per Output
Dynamic V
DDQ
Power Supply
Current per Output
Total Power V
DD
Supply
Current
Total Power V
DDQ
Supply
Current
Test Conditions
2
V
DDQ
= Max., Reference Clock = LOW
Outputs enabled, All outputs unloaded
V
DDQ
= Max., Reference Clock = LOW
3
Outputs enabled, All outputs unloaded
V
DD
= Max., V
DDQ
= Max., C
L
= 0pF
V
DD
= Max., V
DDQ
= Max., C
L
= 0pF
V
DDQ
= 1.5V, F
REFERENCE CLOCK
= 100MHz,
C
L
= 15pF
V
DDQ
= 1.5V, F
REFERENCE CLOCK
= 250MHz,
C
L
= 15pF
V
DDQ
= 1.5V, F
REFERENCE CLOCK
= 100MHz,
C
L
= 15pF
V
DDQ
= 1.5V, F
REFERENCE CLOCK
= 250MHz,
C
L
= 15pF
3
Typ
20
0.1
10
15
20
25
15
30
Max
30
0.3
20
30
30
Unit
mA
mA
µA/MHz
µA/MHz
I
TOT
mA
40
30
mA
60
I
TOTQ
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Differential Input AC Test Conditions for HSTL
Symbol
V
DIF
V
X
V
THI
t
R
, t
F
Input Signal Swing
1
Differential Input Signal Crossing Point
2
Input Timing Measurement Reference Level
3
Input Signal Edge Rate
4
Parameter
Value
1
750
Crossing Point
1
Units
V
mV
V
V/nS
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in automatic test equipment (ATE) environment. Compliant devices
must meet the V
DIF
(AC) specification under actual use conditions.
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must
meet the V
X
specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/nS or greater is to be maintained in the 20% to 80% range of the input waveform
.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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